AI's Trillion Dollar Traffic Jam: Why NEA is Investing in Positron AI

We are in the midst of one of the largest infrastructure projects in human history. Since the GPT-3 moment, the LLM arms race has proliferated at a massive scale, with companies moving rapidly to build more powerful models, chips, networks, and power in a rush to capture share at the intelligence frontier.  AI capex will exceed $1T this year, per Goldman Sachs estimates, while spend on accelerators alone will surpass $1T by the end of the decade, according to Bank of America.  Yet even this historic flood of capital cannot keep pace with demand. Across virtually every link in the supply chain, capacity is being consumed faster than it can be built. SK Hynix CEO Kwak Noh-Jung recently underscored the severity of the shortage: “We still forecast that customer demand will remain higher than our supply capacity even beyond 2030.”¹ 

All this capital is chasing a workload that is fundamentally changing shape–training built the AI infrastructure industry, inference is rapidly becoming its center of gravity, and the two workloads behave nothing alike.  As models grow larger, agents run longer, context windows stretch, each additional token shifts the bottleneck away from raw compute and toward memory bandwidth and capacity. The infrastructure built for the training era is not fit for inference. This is why we’re thrilled to announce NEA’s lead investment in Positron AI’s Series C financing. We’re thrilled to be joined by an exceptional group of co-leads: Valor, Atreides, Andra, Semianalysis Capital, and Jim Clark, along with notable strategics HRT, Cisco, Naver, and others. 

The shift from training to inference has exposed two core cracks in existing architecture.

1. The Memory Wall. Over the past decade, FLOPs have scaled 120x² while memory bandwidth, just 17x³. We have spent a decade making chips extraordinarily good at math while largely neglecting their ability to get the numbers to the mathematician. Training is often compute-bound, so more FLOPs generally meant more performance. Inference turns that assumption on its head. During decode, before a chip can generate each token, it has to pull model weights and the KV cache from memory. Suddenly, the world’s most expensive arithmetic units are sitting around waiting for a delivery. Compute is no longer the scarce resource; feeding it is.

2. The second crack appears even when memory itself isn’t the bottleneck. If bandwidth were the only problem, you’d expect HBM to be running flat out. Instead, real production clusters often achieve less than 30% of theoretical roofline. The culprit is increasingly the network between the chips. 

Why? Models have become too large to live on a single accelerator, forcing them to be sharded across ever-larger meshes of XPUs. Weights and KV cache spill across an expanding mesh of accelerators, forcing every token to coordinate work across chip boundaries. Those interconnects are far slower than local memory, so the result is that compute waits on memory, memory waits on the network, and a very expensive cluster spends a surprising amount of its time waiting on data and itself, rather than utilizing its expensive compute. 

Mixture-of-experts architectures compound this further: experts are increasingly distributed across chips, turning every MoE layer into an all-to-all communication chatter over scale-up links roughly an order of magnitude slower than HBM. Each synchronization stalls compute and strands memory, and this cost only grows as model size and context length continue to outpace any single chip's HBM capacity. 

The bigger the models get, the more time our fastest chips spend talking instead of thinking. And the more experts they add, the more chips join the conversation.

Enter Positron AI.

Positron AI is the next-generation chip company designing silicon from first principles to crack memory and networking walls that define modern AI inference workloads. Led by  CEO, Mitesh Agrawal (fmr. COO of Lambda), and CTO, Thomas Sohmers (fmr. Director of Product, Groq), and joined by elite engineers from Groq, Lambda, Nvidia, Amazon and F5 Networks, Positron AI is rebuilding the infrastructure stack around where future inference workloads are actually headed.

We believe Positron AI has the team and architecture to set the frontier for inference performance, at a fraction of the cost and power. Below are the bets Thomas and Mitesh are making that made us fall in love with Asimov, their upcoming custom silicon, taping out on TSMC N3P.

1. Locality solves both walls. Positron’s core architectural bet is to keep more of the model local. Increasing memory capacity per accelerator keeps more weights and KV cache in directly attached memory, reducing traffic between chips and the need to spread a model across additional accelerators. Increasing memory capacity per chip attacks both by keeping more weights and KV cache local so it never has to cross an interconnect at all. Locality turns a networking problem back into a memory-access problem.

   But that only works if local memory is both fast enough and large enough. HBM solves the former problem but struggles with the latter; LPDDR5X historically had the opposite tradeoff. Positron AI’s custom memory module is designed to collapse that tradeoff, delivering ~10× the bandwidth of conventional LPDDR5X interfaces and effective bandwidth exceeding realized HBM3E, while scaling to 2.3 TB of memory per chip. The result is a fundamentally different scaling curve: higher bandwidth to keep the compute fed, higher capacity to keep the model local, less pressure to scale out.

2. When chips do need to talk, make it cheap. Locality can minimize communication, but it cannot eliminate it. Today, meshing thousands of XPUs together typically means routing traffic through layers of specialized switching ASICs from NVIDIA and Broadcom. At frontier scale, that networking layer can consume 10–25%+ of cluster capex and power, while the switches themselves increasingly require the same liquid-cooling infrastructure as the accelerators they connect.⁴ 

   Positron AI takes a more radical approach: remove the switch. Its switchless fabric directly connects 16,000+ Asimov chips across a range of topologies, with no external NICs or switches. Despite eliminating an entire layer of infrastructure, the fabric delivers 32 Tbps of bidirectional bandwidth per chip, ahead of 28.8 Tbps for SOTA NVLink 6.0.5 All this while removing an entire layer of hardware, power, cooling from the rack. Positron AI’s first bet is to make chips talk less; its second is to make every conversation cheaper.

3. Circumventing HBM and CoWoS compounds the economics and delivers state of the art TCO and Power. The same decisions that improve inference performance also attack its two most expensive supply-chain bottlenecks: HBM and CoWoS. LPDDR variants account for >30% of annual DRAM bit supply, versus roughly 9% for HBM, giving Positron AI access to a far deeper memory supply base at materially lower cost per GB. It also means Asimov does not compete for scarce HBM allocation from Micron, Samsung, or SK Hynix.

   Additionally, Asimov is designed to use conventional packaging, aiming to avoid the cost and capacity constraints of CoWoS. Cheaper memory, simpler packaging, less networking, and lower power should all ultimately flow through to the same place: superior performance and structurally lower TCO.

Positron AI’s  architectural bets ultimately converge on two metrics that matter: tokens per dollar and tokens per watt. In Positron’s simulation, Asimov delivers 5× more tokens per dollar and tokens per watt than NVIDIA Rubin, while drawing just 400W versus Rubin’s 2.3kW.⁶ Positron has also demonstrated its ability to ship. Atlas, its first FPGA-based inference system, is already being deployed in Oracle Cloud Infrastructure. Asimov is the next step: bringing the company’s architecture to custom silicon.

There is precedent for this kind of architectural reset. Google built the infrastructure for web-scale search not by buying better mainframes. They made commodity hardware outperform them. Positron AI is making the same kind of bet for inference: don’t build a better system around HBM, CoWoS, and increasingly elaborate and expensive networks—build one that needs less of them in the first place.

As the Positron AI team moves from Atlas in production to the first Titan racks powered by Asimov in 2027, we’re proud to partner with them. The last computing era was defined by architectures that turned commodity hardware into extraordinary systems–we believe Positron AI is doing it again.